Optimization of a power mosfet and its monolithically integrated self-powering circuits

Issue title: OIPE 2010

Article type: Research Article

Authors: Nguyen-Xuan, H.^{a; *} | Gerbaud, L.^a | Rouger, N.^a | Crébier, J.-C.^a

Affiliations: [a] Grenoble Electrical Engineering Lab (G2ELab), Saint-Martin-d'Hères Cedex, France

Correspondence: [*] Corresponding author: H. Nguyen Xuan, Grenoble Electrical Engineering Lab (G2ELab), UMR 5529 BP 46 - 38402 Saint-Martin-d'H\`{e}res Cedex, France. Tel.: +33 (0)4 76 82 64 77; Fax: +33 (0)4 76 82 63 00; E-mail: Hoa.Nguyen-Xuan@g2elab.grenoble-inp.fr

Abstract: The paper presents a physical structure optimization of an integrated semiconductor device: a power MOSFET and other vertical transistors are integrated within the same die, introducing a novel self supplied power transistor. This integrated optimal design leads to complex optimization problems with close constraints. The main constraint model deals with the avalanche phenomenon that is formulated by multiple integral expressions of implicit functions. The paper focuses on two aspects: the integral formulation of the avalanche model and more specifically its gradient computation in the aim of applying a gradient-based optimization algorithm, and the comparisons of several optimization methods on this problem.

Keywords: Design of monolithically integrated circuits, genetic optimization algorithms, gradient-based optimization algorithm, semiconductor integration constraint, power MOSFET

DOI: 10.3233/JAE-2011-1387

Journal: International Journal of Applied Electromagnetics and Mechanics, vol. 37, no. 2-3, pp. 159-171, 2011