Affiliations: School of Electrical & Electronics Engineering (SEEE), SASTRA Deemed University, Thirumalaisamudram, Thanjavur, India
Correspondence:
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Corresponding author. Siva Janakiraman, School of Electrical & Electronics Engineering (SEEE), SASTRA Deemed University, Thirumalaisamudram, Thanjavur, India. E-mail: siva@ece.sastra.edu.
Abstract: Digitized forms of images do widely used for medical diagnostics. To maintain the privacy of an individual in e-health care applications, securing the medical image becomes essential. Hence exclusive encryption algorithms have been developed to protect the confidentiality of medical images. As an alternative to software implementations, the realization of image encryption architectures on hardware platforms such as FPGA offers significant benefit with its reconfigurable feature. This paper presents a lightweight image encryption scheme for medical image security feasible to realize as concurrent architectural blocks on reconfigurable hardware like FPGA to achieve higher throughput. In the proposed encryption scheme, Lorentz attractor’s chaotic keys perform the diffusion process. Simultaneously, the pseudo-random memory addresses obtained from a Linear Feedback Shift Register (LFSR) circuit accomplishes the confusion process. The proposed algorithm implemented on Intel Cyclone IV FPGA (EP4CE115F29C7) analyzed the optimal number of concurrent blocks to achieve a tradeoff among throughput and resource utilization. Security analyses such as information entropy, histogram, correlation, and PSNR confirms the algorithm’s encryption quality. The strength of diffusion keys was ensured by randomness verification through the standard test suite from the National Institute of Standards and Technology (NIST). The proposed scheme has a larger keyspace of 2384 that guarantees good confusion through near-zero correlation, and successful diffusion with a PSNR of <5 dB towards the statistical attacks. Based on the hardware analysis, the optimal number of concurrent architectural blocks (2 N) on the chosen FPGA to achieve higher throughput (639.37 Mbps), low power dissipation (138.85 mW), minimal resource utilization (1268 Logic Elements) and better encryption quality for the proposed algorithm is recommended as 4 (with N = 2).
Keywords: Concurrency, lightweight, lorentz attractor, FPGA and encryption
