Vedic multiplication based efficient OFDM FFT processor

Issue title: Soft computing and intelligent systems: Tools, techniques and applications

Guest editors: Sabu M. Thampi and El-Sayed M. El-Alfy

Article type: Research Article

Authors: Kalra, Bhawna^* | Sharma, J.B.

Affiliations: Rajasthan Technical University, Kota, Rajasthan, India

Correspondence: [*] Corresponding author. Bhawna Kalra, Rajasthan Technical University, Kota, Rajasthan, India. Tel.: +91 9462396448; E-mail: bhawna.kalra1993@gmail.com.

Abstract: In multi carrier OFDM systems parameters like speed, throughput and hardware area can be improved by using efficient Fast Fourier Transform approach. In this paper an area efficient and high speed 32 bit floating point FFT processor for OFDM using Vedic multiplication process is presented. Proposed FFT processor is based on memory based architecture and utilizing Urdhavatiraykbhyam sutra for Vedic multiplication. As the number of inbuilt multipliers available in FPGAs are limited, hence external multiplication module are required in the multicarrier OFDM systems, in order to reduce the complexity of FPGA implementation. By the use of Vedic multiplication process in FFT of OFDM high throughput with smaller area can be achieved. Simulation results explain that the proposed scheme is having high speed and throughput.

Keywords: FFT, OFDM, Vedic multiplication

DOI: 10.3233/JIFS-169255

Journal: Journal of Intelligent & Fuzzy Systems, vol. 32, no. 4, pp. 3121-3128, 2017