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This journal publishes papers on a number of topics ranging from design to practical experiences with operational high performance/speed networks.
The topics covered will include but not be limited to:
- Communication network architectures
- Evolutionary networking protocols, services and architectures
- Network Security
Authors: Haas, Zygmunt | Gitlin, Richard D.
Article Type: Research Article
Abstract: The very high-speed access requirement that characterizes interactive and real-time high-performance applications like parallel processing, compressed video, or high-quality imaging, initiated a considerable interest in networks that provide a single user with a very high-speed network access. Coupled with this effort is the belief that optical networking can provide very high speed access, in addition to already utilized large aggregated bandwidth. In this paper, we examine the possibility of harvesting the optical spectrum to provide high-speed access networking capability in local-area environment in a way that is economically justifiable. In particular, we describe a design of the physical layer of …an “almost-all” optical local-area network that is capable of providing gigabit per second network access. The network design is based on the dual-bus topology, the field-coding technique that was reported by us earlier (in which the header and the data fields are encoded at different rates), and the principle of “almost-all” optical switching. The field-coding technique allows integration of several subnets on the same physical medium. Moreover, we show that because of the field-coding technique, the maximal number of stations on the bus before signal amplification is required is doubled in the limit. Furthermore, we discuss various implementation issues in the design of ODC, like opto-electronic amplification, clock distribution and clock-data synchronization, and reduction in the receiver dynamic range. Show more
Keywords: All-Optical Networks, Gigabit Networh, Field Coding, Bus Networks
DOI: 10.3233/JHS-1992-1301
Citation: Journal of High Speed Networks, vol. 1, no. 3, pp. 193-214, 1992
Authors: Bahk, Saewoong | El Zarki, Magda
Article Type: Research Article
Abstract: In this paper we describe briefly a dynamic multi-path routing scheme that has been considered for connection oriented homogeneous high-speed wide area Asynchronous Transfer Mode (ATM) networks. The fundamental objective of the scheme is to bridge the gap between routing and congestion control as the network becomes congested. Because propagation delay far out shadows queueing and transmission delay in high-speed networks, the proposed routing scheme works as a shortest path (minimum hop) first algorithm under light traffic conditions. However as the shortest path becomes congested, the source node uses multiple paths when and if available in order to distribute the …load and reduce packet loss. The scheme is a cross between Alternate Path Routing and Trunk Reservation. We compare the performance of the proposed scheme with the Shortest Path Only Algorithm, the Alternate Path Routing Algorithm, the Random Routing Algorithm, and the Trunk Reservation Scheme. The throughput and packet loss performance are compared via simulations. These have been carried out concentrating on a five-node network, each with varying traffic patterns, the intention being to gain insight into the strengths and weaknesses of the various schemes. Show more
Keywords: ATM, Connection Oriented, Multi-path Routing, Cell Loss, Trunk Reservation
DOI: 10.3233/JHS-1992-1302
Citation: Journal of High Speed Networks, vol. 1, no. 3, pp. 215-236, 1992
Authors: Eng, K. Y. | Pashan, M. A. | Spanke, R. A. | Karoll, M. J. | Martin, G. D. | Obara, H. | Ueda, H.
Article Type: Research Article
Abstract: A prototype 2.5 Gb/s ATM switch fabric has been developed for flexible broadband applications. The prototype configuration supports multiple standard line card interfaces, e.g., STM-1 (155 Mb/s), STM-4c (622 Mb/s) and STM-16c (2.5 Gb/s). The ATM cells are extracted from the payload of these SDH signals and are multiplexed inside the fabric to an internal equivalent cell rate of 2.5 Gb/s. Routing is done subsequently on a cell-by-cell basis according to the cell header address information (VPI and/or VCl). The core fabric of the switch is therefore a 2.5 Gb/s ATM switch. The fabric is designed using the theory of …the Growable Switch Architecture guaranteeing the best possible delay-throughput performance for arbitrary traffic distributions for independent inputs. In this prototype implementation, careful considerations have been given to optimize various aspects such as physical size, physical growth, power consumption, protection switching, maintenance and reliability. The core 2.5 Gb/s fabric prototype can grow from 8 x 8 (supporting up to 128 STM-1 interfaces) to larger sizes (e.g., 64 x 64, supporting up to 1024 STM-1 interfaces). Considerations for substantially larger switch sizes have also been taken into account in the design. Descriptions of our initial prototype and its evolution to larger switch dimensions are discussed. Show more
Keywords: ATM, ATM Switching, Packet Switching, Gigabit Switching, Gigabit Networking
DOI: 10.3233/JHS-1992-1303
Citation: Journal of High Speed Networks, vol. 1, no. 3, pp. 237-253, 1992
Authors: Nilsson, Arne A. | Perros, Harry G. | Lai, Fuyung
Article Type: Research Article
Abstract: We consider a synchronized bufferless Clos ATM switch with input cell processor queues. The arrival process to each input port of the switch is assumed to be bursty and it is modelled by an Interrupted Bernoulli Process. Two classes of cells are considered. Service in an input cell processor queue is head-of-line without preemption. In addition, push-out is used. That is, a high priority cell arriving to a full queue takes the space occupied by the low priority cell that arrived last, as long as the cell is not in service. Each cell processor queue is modeled as a priority …IBP/Geo/1/ K + 1 queue with push-out. We first present an exact analysis of this priority queue. The results obtained are then used in an approximation algorithm for the analysis of the ATM switch. Validation tests using simulation data shows that the approximation algorithm has a good accuracy. Show more
Keywords: ATM Switch, Bufferless Clos, Discrete-Time Queueing, IBP, Push-Out
DOI: 10.3233/JHS-1992-1304
Citation: Journal of High Speed Networks, vol. 1, no. 3, pp. 255-279, 1992
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