Affiliations: Computer Science Department, University of California,
Los Angeles, CA - 90095, USA. indranil@cs.ucla.edu | ACM Unit, Indian Statistical Institute, Kolkata - 700
108, India. bhargab@isical.ac.in | Broadcom Corporation, Santa Clara, CA - 95054, USA.
sheng.zhang@broadcom.com | Department of Computer Science & Engineering,
University of Nebraska-Lincoln, Lincoln, NE - 68588, USA. seth@cse.unl.edu
Note: [] Address for correspondence: ACM Unit, Indian Statistical
Institute, Kolkata - 700 108, India
Abstract: Double-tree-scan (DTS) is a new scan-path architecture that is
deemed to be suitable for low-power testing of VLSI circuits. A full DTS
resembles two complete k-level (k > 0) binary trees whose leaf nodes are
merged pair-wise, and thus consists of exactly N_{k} = 3 × 2^{k} − 2
nodes. In this paper, the problem of planar straight-line embedding of a
"double-tree graph" on a rectangular grid is
investigated and an O(N_{k}) time algorithm for drawing it, is described. The
embedding requires at most 2N_{k} grid points, with an aspect ratio lying between
1 and �. Next, techniques of embedding a partial DTS is considered when the
number of nodes n ≠ 3 × 2^{k} − 2, for some k. Layouts of
double-tree scan-paths for some benchmark circuits are also presented to
demonstrate the results.
