Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation

Issue title: Application of Concurrency to System Design

Article type: Research Article

Authors: Garnic, O. | Lanchares, J. | Hermida, R.

Affiliations: Department of Computer Architecture, Universidad Complutense de Madrid, 28040 Madrid, Spain

Abstract: This paper is devoted to studying two key issues of the asynchronous pipelines: their performance, and the influence that the position of stages have on the latency of a pipelined asynchronous circuit as a whole. To attain the performance evaluation, we derive expressions of the latency and the cycle time of a linear pipeline as closed-form formulas. To attain the influence of the position, we present some experiments, using the previous closed-form formulas, on different pipelines.

Keywords: Asynchronous circuits, pipeline performance

Journal: Fundamenta Informaticae, vol. 50, no. 2, pp. 155-174, 2002