Journal of Embedded Computing - Volume 1, issue 3

Authors: Macii, Alberto

Article Type: Other

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 303-304, 2005

Authors: Palermo, Gianluca | Silvano, Cristina | Zaccaria, Vittorio

Article Type: Research Article

Abstract: In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized embedded systems. The exploration problem is multi-objective (e.g., energy and delay), so the main goal of this work is to find a good approximation of the Pareto-optimal configurations representing the best energy/delay trade-offs by varying the architectural parameters of the target system. In particular, the paper presents a Design Space Exploration (DSE) framework to simulate the target …system and to dynamically profile the target applications. In the proposed DSE framework, a set of heuristic algorithms have been analyzed to reduce the overall exploration time by computing an approximated Pareto set of configurations with respect to the selected figures of merit. Once the approximated Pareto set has been built, the designer can quickly select the best system configuration satisfying the constraints. Experimental results, derived from the application of the proposed DSE framework to a superscalar architecture, show that the exploration time can be reduced by three orders of magnitude with respect to the full search approach, while maintaining a good level of accuracy. Show more

Keywords: Design space exploration, low-power design, platform-based design, multi-objective optimisation

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 305-316, 2005

Authors: Nikolaidis, S. | Kavvadias, N. | Laopoulos, T. | Bisdounis, L. | Blionas, S.

Article Type: Research Article

Abstract: A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel …each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way. Show more

Keywords: Instruction-level energy modeling, energy characterization, instantaneous current measurement, microprocessor

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 317-324, 2005

Authors: Ayala, José L. | López-Vallejo, Marisa

Article Type: Research Article

Abstract: This paper presents the design and use of INCAPE (INtegrated Cache Analysis and Power Estimation). The proposed tool integrates an extended analytical model for power estimation in caches within a retargetable cross-design environment. INCAPE has been used to perform experimental design space exploration and analysis of the main factors that strongly impact on the power dissipation of the cache hierarchy. The obtained results validate the usefulness of the proposed methodology and allow the designer to efficiently …design the cache hierarchy when low power constraints are involved. Show more

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 325-340, 2005

Authors: Aa, Tom Vander | Jayapala, Murali | Barat, Francisco | Deconinck, Geert | Lauwereins, Rudy | Corporaal, Henk | Catthoor, Francky

Article Type: Research Article

Abstract: For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. Especially software controlled loop buffers are energy efficient. However current compilers do not fully take advantage of the possibilities of such loop buffers. This paper presents an algorithm to explore for an application or a set of applications what is the optimal loop buffer configuration and the optimal way to use this configuration. Results for the …MediaBench application suite show an additional 35% reduction (on average) in energy in the instruction memory hierarchy as compared to traditional approaches to the loop buffer without any performance implications. Show more

Keywords: Low power design, memory hierarchies, instruction memories, loop buffer, loop cache, design space exploration, multimedia applications, embedded systems

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 341-351, 2005

Authors: Tatas, K. | Soudris, D. | Thanailakis, A.

Article Type: Research Article

Abstract: An optimization methodology that combines high-level exploration with Register Transfer Level (RTL) design for the power-efficient estimation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implementing an optimum on-chip memory hierarchy inside the FPGA, and moving the bulk of required memory transfers from the internal memory hierarchy instead of the external memory. A case study of three popular multimedia kernels is …performed for a number of different FPGA devices. Comparisons among implementations with and without this optimization, prove that great power efficiency can be achieved while satisfying performance constraints. Show more

Keywords: Motion estimation, low-power, FPGA implementation

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 353-362, 2005

Authors: Ferentinos, V. | Geelen, B. | Lafruit, G. | Milia, M. | Bormans, J. | Catthoor, F. | Stouraitis, T.

Article Type: Research Article

Abstract: Powerful multimedia applications are running more and more on very compact and resource-scarce, portable systems. As a consequence, system design optimization, its associated time-to-market constraints and the required automated tool support are becoming increasingly important issues, especially in situations where product derivatives and extensions introduce unforeseen and possibly dramatic constraints in the system optimization process. Nevertheless, the system designer remains an irreplaceable cornerstone for steering the whole system optimization process. …This paper presents the relationship of aforementioned aspects in the context of optimizing data access to memory, which is the dominant factor determining the system-on-a-chip area, data throughput and power consumption. The case study of a 1D and 2D forward and inverse wavelet transform, interacting with surrounding system modules imposed by current multimedia compression standards, leads the reader through the peculiar technical counter-measures and script-based optimization steps to be followed for reaching a satisfactory global optimization. In particular, the data dependencies between the different functional modules are shown to be crucial in the memory optimization process and lead to non-trivial/counter-intuitive decision takings that can increase the energy consumption gains compared to more commonly-accepted, though suboptimal approaches. An example is the counter-intuitive observation that though JPEG2000 uses independently entropy coded blocks over its wavelet subbands, it requires more memory because of "hidden" data dependencies, than its zero-tree based MPEG-4 counterpart, whose intricate entropy coding spreads over all the subbands. Hence, to achieve an overall optimal implementation with good trade-offs between efficiency and cost, it is strongly suggested that algorithmic and implementation designers should co-operate in early stages of the multimedia systems design, facilitated by high-level memory cost estimation analyses. Show more

Keywords: Lower power, multimedia, complexity analysis, time-to-market, memory compaction

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 363-380, 2005

Authors: Acquaviva, Andrea | Simunic, Tajana | Deolalikar, Vinay | Roy, Sumit

Article Type: Research Article

Abstract: This paper presents a new power management technique aimed at increasing the energy efficiency of client-server multimedia applications running on wireless portable devices. We focus on reducing the energy consumption of the wireless network interface of the client by allowing the remote server to control the power configuration of the network card depending on the workload. In particular, we exploit server knowledge of the workload to perform an energy-efficient traffic reshaping, without compromising on the …quality of service. We tested our methodology on the SmartBadge IV wearable device running an MPEG4 streaming video application. Using our technique we measured energy savings of more than 67% compared to no power management being used on the WLAN interface. In addition, we save as much as 50% of energy with respect to the standard 802.11b power management. All of the energy savings are obtained with no performance loss on the video playback. Show more

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 381-389, 2005

Authors: Gilbert, Frank | Vogt, Timo | Wehn, Norbert

Article Type: Research Article

Abstract: The outstanding forward error correction provided by Turbo-Codes made them part of today's and emerging communications standards. Therefore, efficient Turbo-Decoder architectures are important building blocks in communications systems. In this paper we present a scalable, highly parallel architecture for UMTS compliant Turbo decoding and apply architecture-driven voltage scaling to reduce the energy consumption. We will show that this approach adds some additional, more energy-efficient solutions to the design space of low power …Turbo decoding systems. It can save up to 34% of the decoding energy per datablock under realistic voltage assumptions. We present throughput, area, and energy results for various degrees of parallelization based on synthesis on a 0.18 μm ASIC-technology library, which is characterized for two different supply voltages: nominal 1.8 V and nominal 1.3 V. Show more

Keywords: Low energy, voltage scaling, mobile communication, channel coding, Turbo-Codes

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 391-402, 2005

Authors: Miclea, Liviu | Enyedi, Szilárd | Prinetto, Paolo | Benso, Alfredo

Article Type: Research Article

Abstract: This article demonstrates how to use intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (Built-In Self-Test) and BISR (Built-In Self-Repair) facilities. Agents are software modules that perform monitoring, diagnosis and repair of the faults. They form together a society whose members communicate, set goals and solve tasks. An experimental solution is presented, and future developments of the proposed approach are explored.

Keywords: Intelligent agent, distributed BIST, BISR, self-repair, Java

Citation: Journal of Embedded Computing, vol. 1, no. 3, pp. 405-414, 2005