A simulation study for the performance of an on‐board ATM switching scheme for broadband satellite communications network

Article type: Research Article

Authors: Yoshimura, Naoko | Kadowaki, Naoto

Affiliations: Communications Research Laboratory, M.P.T. Japan, 4‐2‐1 Nukui‐Kitamachi Koganei, Tokyo 184‐8795, Japan Tel.: +81 42 327 5336; Fax: +81 42 327 6825; E‐mail: yosshiy@crl.go.jp

Note: [] Corresponding author.

Abstract: A high data rate (HDR) satellite communication system is essential for developing the network configuration of a Global Information Infrastructure (GII) because of its features, such as wide area coverage, flexibility of network configuration and multicast connection capability. From this point of view, Communications Research Laboratory (CRL) is conducting research and development of a Gigabit satellite system [1] that has an on‐board ATM switch and gigabit‐class capacity. We have developed a hardware simulator in order to investigate how satellite links influence on‐board ATM switching and network performance, such as a long delay and burst error. In this paper, we describe the simulation results for the TCP layer performance and the SVC connection set‐up performance.

Journal: Space Communications, vol. 17, no. 1,2,3, pp. 137-141, 2001