Affiliations: Communications Research Laboratory, 4‐2‐1, Nukui‐kitamachi, Koganei, Tokyo 184‐8795, Japan Tel.: +81 42 327 7510; Fax: +81 42 327 6697; E‐mail: staira@crl.go.jp | Advanced Space Communications Research Laboratory (ASC), 7F Hayakawa‐Tonakai Bldg., 2‐12‐5, Iwamoto‐cho, Chiyoda‐ku, Tokyo 101‐0032, Japan Tel.: +81 3 5821 5088; Fax: +81 3 5821 5096; E‐mail: takeda@asc.co.jp, kawakami@asc.co.jp
Abstract: An on‐board processor makes efficient use of the channel capacities in a satellite communications system employing multibeam technology, and an on‐board processor has been developed for the Engineering Test Satellite Eight (ETS‐VIII) which is an experimental satellite for a multibeam mobile satellite communications system. This communications system uses multicarrier TDMA. Such multiple access systems are, however, in certain cases subject to on‐board processor internal congestion. This paper describes the results of computer simulation studies of the traffic capacity obtained using three baseband switching methods: carrier switching, slot switching, and simultaneous‐slot switching, when beams for mobile links are allocated into two dimensions. The studies indicate that the probability of internal congestion due to the TDMA system is very small when the simultaneous‐slot switching method is used, and that simultaneous‐slot switching is beneficial for the on‐board processor of the multicarrier TDMA system.
