Affiliations: The Pennsylvania State University, University Park, PA, USA. E-mails: {wzd109, kandemir}@cse.psu.edu | Intel Corporation, University Park, PA, USA. E-mail: yuanrui.zhang@intel.com | Northwestern University, Evanston, IL, USA. E-mail: sson@eecs.northwestern.edu
Abstract: File layout of array data is a critical factor that effects the behavior of storage caches, and has so far taken not much attention in the context of hierarchical storage systems. The main contribution of this paper is a compiler-driven file layout optimization scheme for hierarchical storage caches. This approach, fully automated within an optimizing compiler, analyzes a multi-threaded application code and determines a file layout for each disk-resident array referenced by the code, such that the performance of the target storage cache hierarchy is maximized. We tested our approach using 16 I/O intensive application programs and compared its performance against two previously proposed approaches under different cache space management schemes. Our experimental results show that the proposed approach improves the execution time of these parallel applications by 23.7% on average.
