Evaluating multicore algorithms on the unified memory model

Issue title: Software Development for Multi-core Computing Systems

Article type: Research Article

Authors: Savage, John E.^; | Zubair, Mohammad

Affiliations: Brown University, Providence, RI 02912, USA | Old Dominion University, Norfolk, VA 23529, USA

Note: [] Corresponding author. Tel.: +1 401 863 76 42; Fax: +1 401 863 76 57; E-mail: jes@cs.brown.edu.

Abstract: One of the challenges to achieving good performance on multicore architectures is the effective utilization of the underlying memory hierarchy. While this is an issue for single-core architectures, it is a critical problem for multicore chips. In this paper, we formulate the unified multicore model (UMM) to help understand the fundamental limits on cache performance on these architectures. The UMM seamlessly handles different types of multiple-core processors with varying degrees of cache sharing at different levels. We demonstrate that our model can be used to study a variety of multicore architectures on a variety of applications. In particular, we use it to analyze an option pricing problem using the trinomial model and develop an algorithm for it that has near-optimal memory traffic between cache levels. We have implemented the algorithm on a two Quad-Core Intel Xeon 5310 1.6 GHz processors (8 cores). It achieves a peak performance of 19.5 GFLOPs, which is 38% of the theoretical peak of the multicore system. We demonstrate that our algorithm outperforms compiler-optimized and auto-parallelized code by a factor of up to 7.5.

Keywords: Option pricing, memory hierarchy, multicore chips

DOI: 10.3233/SPR-2009-0290

Journal: Scientific Programming, vol. 17, no. 4, pp. 295-308, 2009