Affiliations: Department of Computer Science, University of Utah, Salt Lake City, UT 84112, USA | Intel Corporation, Dupont, WA 98327, USA
Note: [] Corresponding author: Prof. John Carter, Department of Computer Science, 50 S Central Campus Drive, Room 3190, University of Utah, SLC, UT 84112‐9205, USA. Tel.: +1 801 585 5474; Fax: +1 801 581 5843; E‐mail: retrac@cs.utah.edu.
Abstract: Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application‐specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can improve the performance of memory‐bound scientific applications. For instance, Impulse decreases the running time of the NAS conjugate gradient benchmark by 67%. We expect that Impulse will also benefit regularly strided, memory‐bound applications of commercial importance, such as database and multimedia programs.
