JIST: Just-In-Time scheduling translation for parallel processors

Article type: Research Article

Authors: Agosta, Giovanni | Reghizzi, Stefano Crespi | Falauto, Gerlando | Sykora, Martino

Affiliations: Politecnico di Milano, Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32 - 20133 Milano, Italy. E-mail: {agosta, crespi, sykora}@elet.polimi.it

Note: [] Corresponding author

Abstract: The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JIST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JITcompiler. Further optimizations are discussed.

Journal: Scientific Programming, vol. 13, no. 3, pp. 239-253, 2005