Affiliations: Coordinated Science Laboratory, University of Illinois
at Urbana-Champaign, 1308 W. Main Street, Urbana, IL 61801, USA. E-mail:
dsn@csrd.uiuc.edu | Department d' Arquitectura de Computadors, Universitat
Politecnica de Catalunya, c/Jordi Girona 1-3, Modul D6, Barcelona 08034,
Spain. E-mail: {ernest, eduard, jesus}@ac.upc.es
Note: [] Corresponding author. Present address: Department of Computer
Science, The College of William&Mary, McGlothlin Street Hall, Williamsburg,
VA 23187-8795, USA. Tel.: +1 757 221 3455; Fax: +1 757 221 1717
Abstract: In this paper we explore the idea of customizing and reusing loop
schedules to improve the scalability of non-regular numerical codes in
shared-memory architectures with non-uniform memory access latency. The main
objective is to implicitly setup affinity links between threads and data, by
devising loop schedules that achieve balanced work distribution within
irregular data spaces and reusing them as much as possible along the execution
of the program for better memory access locality. This transformation provides
a great deal of flexibility in optimizing locality, without compromising the
simplicity of the shared-memory programming paradigm. In particular, the
programmer does not need to explicitly distribute data between processors. The
paper presents practical examples from real applications and experiments
showing the efficiency of the approach.
Keywords: OpenMP, shared-memory programming models, page placement, data and computation affinity
