Affiliations: [a] V.S.B. Engineering College, Karur, Tamilnadu, India
| [b] Erode Sengunthar Engineering College, Erode, Tamilnadu, India
| [c] M. Kumarasamy College of Engineering, Karur, Tamilnadu, India
Correspondence:
[*]
Corresponding author. K. Kalaichelvi, V.S.B. Engineering College, Karur –639 111, Tamilnadu, India. E-mail: kalaish123@gmail.com.
Abstract: The research tends to suggest a spin-orbit torque magnetic random access memory (SOT-MRAM)-based Binary CNN In-Memory Accelerator (BIMA) to minimize power utilization and suggests an In-Memory Computing (IMC) for AdderNet-based BIMA to further enhance performance by fully utilizing the benefits of IMC as well as a low current consumption configuration employing SOT-MRAM. And recommended an IMC-friendly computation pipeline for AdderNet convolution at the algorithm level. Additionally, the suggested sense amplifier is not only capable of the addition operation but also typical Boolean operations including subtraction etc. The architecture suggested in this research consumes less power than its spin-orbit torque (STT) MRAM and resistive random access memory (ReRAM)-based counterparts in the Modified National Institute of Standards and Technology (MNIST) data set, according to simulation results. Based to evaluation outcomes, the pre-sented strategy outperforms the in-memory accelerator in terms of speedup and energy efficiency by 17.13× and 18.20×, respectively.
Keywords: Energy efficiency, IMC, SOT-MRAM, speedup
