Affiliations: Department of Electrical and Electronics Engineering, Shiraz University of Technology, Modarres Boulevard, Shiraz, Iran
Correspondence:
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Corresponding author. Ebrahim Abiri, Department of Electrical and Electronics Engineering, Shiraz University of Technology, Modarres Boulevard, Shiraz, Iran. Tel.: +98 9123708599; Fax: +98 7137353502; E-mail: abiri@sutech.ac.ir.
Abstract: The memory includes flip flap cells which can store binary information. Therefore by designing the binary storing cell, which has the low chip area and power consumption, the high capacity memories with high performance can be presented. The gate diffusion input (GDI) method employed in designing low power logic gates can decrease the chip area and parasitic and interconnection capacitors. In this paper, the modified-GDI (m-GDI) method is used based on a basic GDI method in order to design master-slave D-Flip Flap (M/S-DFF) circuit. By employing the presented M/S-DFF circuit and the Boolean functions of m-GDI method, Random Access Memory (RAM) cell is designed. For optimizing the performance of the proposed memory cell and gaining the minimum power and propagation delay, the transistors size is adjusted with non-dominated sorting genetic algorithm-II (NSGA-II) in MATLAB software. Finally, the 4-words×4-bits RAM (4×4 RAM) cell is designed and evaluated by employing optimized RAM cell with algorithm. Due to the achieved results, the power consumption of the 4×4 RAM cell is 72.3% , while its propagation delay and Power-Delay Product (PDP) criterion are decreased 75.9% and 93% , respectively, in compare with similar cells which aren’t optimized. The circuit simulation is done with Synopsys H-SPICE simulator in 32 nm CNTFET technology. For ensuring the accurate function of this algorithm, it is experimented on memory cell and decoder. By comparing NSGA-II algorithm with Multiple Objective Particle Swarm Optimization (MOPSO) algorithm, it can be observed that this method has good ability in multi-objective optimization.
