VLSI implementation of a real time fuzzy processor

Article type: Research Article

Authors: Cardarilli, G.C. | Re, M. | Lojacono, R.

Affiliations: Department of Electronics, University of Rome “Tor Vergata”, Via della Ricerca Scientifica, 1, 00133-Rome, Italy. E-Mail: g.cardarilli@ieee.org, marco.re@ieee.org, lojacono@ing.uniroma2.it

Abstract: In this paper, the realization of a new fuzzy processor is described. Original approaches are used for the implementation of both the fuzzifier and defuzzifier. The fuzzifier architecture is simplified by using input membership functions of suitable shape. The robustness of the fuzzy inference mechanism well tolerates this simplification. The defuzzifier uses the Center of Gravity (COG) method whose performance is improved by a new look-up table based computation. Moreover, the whole system has been simplified by accepting small approximations in the evaluation of the more expensive arithmetic operations. These approximations are obtained by supposing some constraints on the input values and imply small errors in the final results. The proposed architecture is very efficient and its implementation requires small area. In fact, the layout of the processor, using a 1 μm CMOS technology, requires only 7 mm2 of silicon area. A speed greater than 100 KFLIPS is obtained with a 20 MHz clock. As consequence, this architecture can be used as a core cell in complex system integrating a whole processing structure.

Journal: Journal of Intelligent and Fuzzy Systems, vol. 6, no. 3, pp. 389-401, 1998