Affiliations: School of Information Technology and Engineering,
Faculty of Engineering, University of Ottawa, Ottawa, Ontario K1N 6N5, Canada,
and Department of Computer and Information Science, Troy State University
Montgomery, Montgomery, AL 36103, USA | School of Information Technology and Engineering,
Faculty of Engineering, University of Ottawa, Ottawa, Ontario K1N 6N5,
Canada | Department of Computer and Information Science, Troy
State University Montgomery, Montgomery, AL 36103, USA
Abstract: The realization of space-efficient support hardware for built-in
self-testing (BIST) is of great importance in the design and manufacture of
VLSI circuits. Novel approaches to designing aliasing-free space compaction
hardware were recently proposed in the context of testing cores-based
system-on-chip (SOC) for single stuck-line faults, extending the well-known
concepts of conventional switching theory, specifically those of cover table
and frequency ordering commonly utilized in the simplification of switching
functions, and of compatibility relation as used in the minimization of
incomplete sequential machines, based on optimal generalized sequence
mergeability, as developed and utilized by the authors in earlier works. The
advantages of these aliasing-free compaction methods over earlier techniques
are quite obvious, since zero-aliasing is achieved without any modifications of
the module under test (MUT), while keeping the area overhead and signal
propagation delay relatively low as contrasted with the conventional parity
tree linear compactors. Besides, the approaches could be applied with both
deterministic compacted and pseudorandom test patterns. The subject paper,
without furnishing details of the different algorithms developed in the
implementation of these approaches to designing zero-aliasing space compactors,
provides the mathematical basis of selection criteria for merger of an optimal
number of outputs of the MUT to achieve maximum compaction ratio in the design,
along with some results from simulation experiments conducted on ISCAS 85
combinational and ISCAS 89 full-scan sequential benchmark circuits, with
simulation programs ATALANTA, FSIM, and HOPE.
Keywords: Aliasing-free (zero-aliasing) space compaction, built-in self-testing (BIST) in VLSI, compatibility of response data outputs, cores-based system-on-chip (SOC), module under test (MUT)
