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Article type: Research Article
Authors: Hosseinzadeh, Mehdi | Reshadi, Midia | Khademzadeh, Ahmad | Navi, Keivan
Affiliations: Science and Research Branch, Islamic Azad University, Tehran, Iran | Iran Telecommunication Research Center, Tehran, Iran | Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran
Abstract: Residue Number System (RNS) is an integer and non weighted number system that is useful tool for Digital Signal Processing (DSP) since it can support parallel, carry-free, high-speed and low power arithmetic. Redundant Residue Number System is an extension of RNS which also supports error detection and correction. The Multi-Level Residue Number System uses the new Residue Number System for each modulo, so in the relation of decreasing modulo the speed of operation is increased. By the combination of those systems we purpose a new numeric system which supports parallel and high speed computations, restricted carry propagation and reliable communications. This system also supports high error detection and correction capabilities. Because of design challenge of future nanoscale regime, on-chip networks have been proposed as a solution. As technology scales toward deep submicron, on-chip interconnects are becoming more sensitive to noise sources such as crosstalk or power supply noise. Therefore error detection and correction is one of the major properties of future on-chip micro networks. In this paper we propose using Redundant Multi-Level Residue Number System to increase the data transmission reliability in on-chip networks. This method achieves more optimizations in the terms of data security, error detection and correction, high speed data transmission and computation.
Keywords: networks on chip, intra-extra chip level communication, residue number system, error detection and correction, fault tolerant system
Journal: Journal of Integrated Design & Process Science, vol. 12, no. 1, pp. 13-22, 2008
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