Fault tolerant and congestion aware routing algorithm for network on chip¹

Article type: Research Article

Authors: Nehnouh, Chakib^{; *} | Senouci, Mohamed

Affiliations: Lab LAPECI, Department of Computer Science, University of Oran 1, Ahmed Ben Bella, Algeria. E-mails: nahnouhc@yahoo.fr, msenouci@yahoo.fr

Correspondence: [*] Corresponding author. E-mail: nahnouhc@yahoo.fr; Tel.: +213793198130.

Note: [1] Fault Tolerant and Congestion Aware Routing Algorithm for Network on Chip.

Abstract: Continuous technology scaling in semiconductor industry makes the system reliability as a serious concern in the area of nanoscale computing. In this paper, a fully adaptive routing algorithm is proposed to overcome faults in NoCs (Network-on-Chip). This algorithm called DINRA-NoC (DIstiributed and New Routing Algorithm for NoC) is distributed, fault tolerant and congestion-aware. First, each node selects the appropriate output to route packets to neighbor routers according to the state of each link and router. Secondly, the proposed routing algorithm takes in account the status of adjacent routers traffic to update the congestion metric. DINRA-NoC does not use any VCs (Virtual Channels) and is deadlock-free. A simulation of the proposed routing algorithm has been carried out using Noxim simulator. The results show that DINRA ensures a good reliability rate despite of the presence of many faulty routers/links. In other hand, the simulation results indicate that the performance of the proposed routing algorithm surpasses the performance of existing algorithms in terms of lowering the congestion, improving average latency and increasing throughput.

Keywords: Congestion, fault tolerance, reliability, routing algorithm, sub-network

DOI: 10.3233/JHS-190618

Journal: Journal of High Speed Networks, vol. 25, no. 3, pp. 311-329, 2019