Abstract: Low Noise Amplifier (LNA) is the front end block in RF receiver that improves the performance of wideband receivers. These receivers need LNA with high linearity to protect its signals from out-of-band interferences. Linearization is a key factor in LNA that maintains linear operation in the presence of large distracting signals. Existing techniques in LNA design are optimum gate biasing, MGTR, body biasing, noise cancellation, feed forward, derivative superposition, and modified DS technique. The key challenge of RF LNA circuit is to attain high gain and better noise performance with low power consumption without affecting linearity of LNA. This paper presents several linearization methods used in CMOS LNA. These are (1) post distortion, (2) capacitive feedback, (3) resistive feedback, and (4) current reuse technique. We also propose a new method for LNA with resistive and capacitive feedback. In this paper, different LNA circuits and proposed LNA are simulated using 90 nm CMOS technology. Reuse of bias current and two stage coupling by single current source approach in the proposed current reuse LNA with resistive (R) and capacitive (C) feedback yields better gain of 15.2 dB, noise figure of 2.17 dB and power consumption of 7.1 mW with respect to other techniques. The outputs obtained are compared with other similar works. These results validate that the proposed LNA is practically feasible for wireless sensor network applications.
Keywords: Low noise amplifier (LNA), single ended LNA, resistive feedback, capacitive feedback, post distortion linearization technique (PD-LNA), current-reuse technique
