Affiliations: Department of Electrical Engineering, Polytechnic University, Brooklyn, NY, USA
Note: [] Corresponding author: H. Jonathan Chao, Department of Electrical Engineering, Polytechnic University, Six Metrotech Center, Brooklyn, NY 11201, USA. Tel.: +1 718 260 3302; Fax: +1 718 260 3906; E‐mail: chao@antioch.poly.edu.
Abstract: Terabit IP switch router is a key to the success of next generation Internet (NGI) with its backbone capacity supporting exponentially increasing traffic. The challenges in designing a terabit IP switch router include (1) a large capacity switch fabric providing high speed interconnection for a number of smaller capacity router modules, and (2) a fast arbitration scheme resolving output contention within stringent time constraint while achieving high throughput and low delay. In this paper, an input–output buffered switch architecture with a speedup of two is employed; our simulation results show that it can nearly achieve the theoretic bound in average delay/throughput performance of an output buffered switch. We propose a 256\times 256 multicast optical interconnection network (OIN) based on advanced wavelength division multiplexing (WDM) technology as the switch fabric for terabit IP switch routers. Its component and interconnection complexity, and power budget are evaluated. A novel ping‐pong arbitration (PPA) scheme is used to solve the output contention in the OIN. The arbitration time of an N‐input switch can be achieved in the order of \log_4\lceil N/2\rceil. For instance, with N=256 the arbitration can be completed in 11 gates delay, less than 5 ns using the current CMOS technology, showing that the PPA scheme can support multiple terabit/s switch capacity.
