Affiliations: Heinz Nixdorf Institute, University of Paderborn,
Fuerstenallee, 11, D-33102, Paderborn, Germany | C-LAB, University of Paderborn, Fuerstenallee, 11,
D-33102, Paderborn, Germany | Electrical Engineering Department, UFRGS, Av. Osvaldo
Aranha, 103, CEP: 90035-190, Porto Alegre, Brazil | Heinz Nixdorf Institute, University of Paderborn,
Fuerstenallee, 11, D-33102, Paderborn, Germany
Abstract: High computational performance and flexibility are the requirements
of nowadays embedded systems and they are increasing constantly. Moreover, a
single architecture must be able to support different applications with
dynamically requirements (changing environments). Reconfigurable computing
based on hybrid architectures, comprising general purpose processor (CPU) and
Field Programmable Gate Array (FPGA), is very attractive because it can provide
high computational performance as well as flexibility to support the
requirements of today's embedded systems. As an Operating System (OS) is
desired to provide support for such systems, it has to use the available
resources in an optimal way (competing with the application), since an embedded
system architecture usually lack of resources. Therefore, we present here our
approach towards a reconfigurable RTOS that is able to distribute itself over a
hybrid architecture (comprising FPGA and CPU). In this work we will present the
main concepts and methods used to achieve the desired RTOS. Moreover, we
present some preliminary evaluation results which show the applicability of our
approach.
