Affiliations: R&D Center, Advanced Digital Chips Inc., 14th Floor,
Instopia Building, 467-23, Dogok-Dong, GangNam-Gu, Seoul 135-270, Korea | School of Engineering, Korea University at Seo-Chang,
Chung-Nam 339-700, Korea
Note: [] Corresponding author: Hyun-Gyu Kim, Ph.D., R&D Center,
Advanced Digital Chips Inc., 14th Floor, Instopia Bldg., 467-23, Dogok-Dong,
GangNam-Gu, Seoul 135-270, Korea. Tel.: +82 2 2107 5891; Fax: +82 2 571 4890;
E-mail: babyworm@gmail.com
Abstract: EISC (Extendable Instruction Set Computer) is a compressed code
architecture developed for embedded applications. In this paper, we propose a
DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We
present how we could exploit the special features, and how we could overcome
the weaknesses, of the EISC architecture to accelerate DSP applications with a
relatively low hardware overhead. Our simulations and experiments show that the
proposed DSP-enhanced processor reduces the average execution times of the DSP
kernels and DSP applications considered in this work, by 42.5% and 31.3%
respectively. The proposed DSP enhancements cost about 10300 gates and do not
affect the operating frequency of the processor. The proposed DSP-enhanced
processor has been embedded in an SoC for video processing and proven in
silicon.
