SH-X: An embedded processor core for consumer appliances

Issue title: Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications

Article type: Research Article

Authors: Arakawa, F. | Ishikawa, M. | Kondo, Y. | Kamei, T. | Nishii, O. | Hattori, T.

Affiliations: Hitachi Ltd., Central Research Laboratory, Tokyo, Japan | Renesas Technology Corporation, Tokyo, Japan

Note: [] Corresponding author. E-mail: arakawa@crl.hitachi.co.jp

Abstract: A SuperH™ embedded processor core SH-X implemented in a 130-nm CMOS process running at 400~MHz achieved 720 MIPS and 2.8 GFLOPS at a power of 250 mW under worst-case conditions. It has a dual-issue seven-stage pipeline architecture, but reaches the 1.8 MIPS/MHz of the previous five-stage processor. The on-chip memory configuration is tuned for digital consumer appliances. A new resume-standby mode enables a standby current of less than 100 μA and a 3-ms recovery time. The processor meets the requirements of a wide range of applications, and is suitable for digital appliances aimed at the consumer market, such as cellular phones, digital still/video cameras, and car navigation systems.

Journal: Journal of Embedded Computing, vol. 2, no. 1, pp. 83-90, 2006