Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy

Issue title: Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications

Article type: Research Article

Authors: Zhang, Wei

Affiliations: Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, IL 62901, USA. E-mail: zhang@engr.siu.edu

Abstract: With the scaling of technology, leakage energy reduction has become increasingly important, especially for cache memories. Recent studies in drowsy instruction cache show that the leakage energy of the instruction cache can be significantly reduced with little performance degradation by exploiting the instruction spatial locality at the cache sub-bank level [5]. To hide the performance penalty due to the sub-bank wake-up latency, a prediction buffer is used to predict and pre-activate the next sub-bank at runtime. However, consulting the prediction buffer at every cache access consumes non-trivial dynamical energy, which can compromise the overall energy savings substantially. This paper presents a more energy-efficient compiler-guided approach to capture the sub-bank transition behavior at link time and to pre-activate the instruction cache sub-bank at runtime based on the compiler-directed hints. We also propose a hybrid approach to exploit both the static and dynamic information for reducing the performance penalty further with little dynamic energy overhead. Our experiments reveal that the static approach is very successful in capturing the sub-bank transition behavior to reduce the performance penalty and it also reduces 38.2% more leakage energy than the hardware-based approach, taking the dynamic energy overhead into account. Moreover, our results show that the hybrid approach is the best strategy for the drowsy instruction cache to balance leakage energy reduction and performance.

Keywords: Drowsy instruction cache, leakage energy, compiler, sub-bank prediction, prediction buffer

Journal: Journal of Embedded Computing, vol. 2, no. 1, pp. 35-48, 2006