Affiliations: KOM Department, Aalborg University, DK-9220 Aalborg,
Denmark | LESTER Laboratory, University of South Brittany,
F-56321 Lorient Cedex, France
Abstract: The objective of this work is to explore the design-space of digital
embedded systems, before the high-level synthesis or compilation steps, in
order to converge towards promising architecture-application matchings. This
paper presents the first step of the "Design-Trotter" framework. This step,
dedicated to the system-level design-space exploration, is performed before the
SoC architecture definition and consists of functional and algorithmic
explorations of the application. The first sub-goal of this work is to exhibit
all the available parallelism of the application by means of an efficient graph
representation. The second sub-goal is to guide the designer by means of
dynamic estimates. These estimates are dynamic since they are represented by
parallelism vs. delay trade-off curves, where a point represents a possible
architecture model in terms of parallelism options for both processing and
data-transfer operations and also for local memory requirements. This paper
presents the original techniques that we have developed and some experiments
that illustrate how the designer can benefit from our work to build or select
an architecture.
