Affiliations: Department of Computer Science, The University of
Texas at Dallas, Richardson, TX 75083, USA | Department of Computer Science, The University of
California at Riverside, Riverside, CA 92521, USA
Abstract: Tag comparison elimination (TCE) is an effective approach to reduce
I-cache energy. Current research focuses on finding good trade-offs between
hardware cost and percentage of comparisons that can be removed. For this
purpose, two low cost innovations are proposed in this paper. We design a small
dedicated TCE table whose size is flexible both horizontally (entry size) and
vertically (number of entries). The design also minimizes interactions with the
I-cache. For a 64-way 16K cache, the new design reduces the tag comparisons to
2.7% with a fraction only 20% of the hardware cost of the way memoization
technique. The result is 50% better compared to a recent proposed low cost
design of comparable hardware cost.
Keywords: Tag comparison elimination, low-power instruction cache