Instruction buffering exploration for low energy embedded processors

Issue title: Low-power Embedded Systems

Article type: Research Article

Authors: Aa, Tom Vander | Jayapala, Murali | Barat, Francisco | Deconinck, Geert | Lauwereins, Rudy | Corporaal, Henk | Catthoor, Francky

Affiliations: KULeuven, ESAT/ELECTA, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium | IMEC vzw, Kapeldreef 75, B-3001, Heverlee, Belgium | TU Eindhoven, Electrical Engineering, Den Dolech 2, 5612 AZ Eindhoven, Netherlands

Note: [] Corresponding author. E-mail: tom.vanderaa@esat.kuleuven.be

Abstract: For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. Especially software controlled loop buffers are energy efficient. However current compilers do not fully take advantage of the possibilities of such loop buffers. This paper presents an algorithm to explore for an application or a set of applications what is the optimal loop buffer configuration and the optimal way to use this configuration. Results for the MediaBench application suite show an additional 35% reduction (on average) in energy in the instruction memory hierarchy as compared to traditional approaches to the loop buffer without any performance implications.

Keywords: Low power design, memory hierarchies, instruction memories, loop buffer, loop cache, design space exploration, multimedia applications, embedded systems

Journal: Journal of Embedded Computing, vol. 1, no. 3, pp. 341-351, 2005