Affiliations: [a] School of Mechano-Electronic Engineering, Xidian University, Xi'an, Shaanxi, China | [b] School of Electronic Engineering and Automation, Guilin University of Electronic Technology, Guilin, Guangxi, China | [c] Guilin University of Aerospace Technology, Guilin, Guangxi, China
Correspondence:
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Corresponding author: Chuanpei Xu, School of Electronic Engineering and Automation, Guilin University of Electronic Technology, Guilin 541004, Guangxi, China. Tel.: +86 773 2191029; Fax: +86 773 2191029; E-mail:mataaedu@outlook.com
Abstract: Efficiently using the limited I/O resources provided by
automatic test equipment (ATE) to test Network-on-Chip (NoC) is a key issue
in NoC test scheduling. Numerous test scheduling approaches for NoC have
been proposed to test the embedded cores. Yet, these approaches commonly
assumed that a whole test access mechanism (TAM) is occupied by an embedded
core during testing. Different from these existing approaches, in this
paper, we propose an approach for efficiently utilizing the TAM resources
for test scheduling in NoC. We make use of the bandwidth division
multiplexed (BDM) strategy, which divides a single TAM into several sub-TAMs
with different width, enables multiple embedded cores share the same TAM to
achieve transmission at the same time, thus maximize the test parallelism.
Then, a refined quantum-inspired evolutionary algorithm (RQEA) strategy,
which incorporates multi-nary and variable population techniques, is
presented to solve the test scheduling problem of NoC. In addition, path
delays, path conflicts and power constraints were taken into consideration.
Experimental results for the ITC'02 SoC test benchmarks show that the new
approach results in substantial reduction in overall test time for a limited
TAM budget, compared to previous works.
Keywords: NoC, TAM, test scheduling, refined quantum-inspired evolutionary algorithm, bandwidth division multiplexed
