Affiliations: [a] Department of ECE, GVP College of Engineering (A), Visakhapatnam, India | [b] Department of ECE, JNTUK UCEV, Vizianagaram, India | [c] Department of ECE, GRIET, Hyderabad, India | [d] Department of CSE, IIITDM Kancheepuram, Tamilnadu, India
Correspondence:
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Corresponding author: Bhaskara Rao Jammu, Department of ECE, GVP College of Engineering (A), Visakhapatnam, India. E-mail: jbhaskararao@gvpce.ac.in.
Abstract: The need to implement high-speed Signal processing applications in which multiplication and division play a vital role made logarithmic arithmetic a prominent contender over the traditional arithmetic operations in recent years. But the logarithm and antilogarithm converters are the bottlenecks. In order to reduce the logarithmic conversion complexity, several works have been introduced from time to time for correcting the error in Mitchell’s algorithm but at the cost of hardware. In this work, we propose a 32-bit binary to the binary logarithmic converter with a simple correction circuit compared with existing techniques. Unlike the current methods that use the linear piece-wise approximation in the mantissa, we propose a weighted average method to correct the error in Mitchell’s approximation. The maximum error percentage from the proposed work is 0.91%, which is 16.9% of Mitchell’s error percentage.
Keywords: Logarithmic arithmetic, logarithmic number system, logarithmic conversion, Mitchells algorithm, error correction, DSP systems
