GA evolved CGP configuration data for digital circuit design on embryonic architecture

Article type: Research Article

Authors: Malhotra, Gayatri^{a; b; *} | Duraiswamy, Punithavathi^b

Affiliations: [a] U R Rao Satellite Centre, Bangalore, India | [b] M. S. Ramaiah University of Applied Sciences, Bangalore, India

Correspondence: [*] Corresponding author: Gayatri Malhotra, U R Rao Satellite Centre, Bangalore, India. E-mail: gayatri@ursc.gov.in.

Abstract: Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or genome data to all the embryonic cells makes each cell capable of selecting required cell function using selective gene. The primary digital circuits of avionics are implemented on the fabric, where the configuration data in Cartesian Genetic Programming (CGP) format is evolved through customized GA. The CGP format is preferred over LUT format for the circuit configuration data due to its fixed data size in case of modular design. Further the CGP format enables fault detection at embryonic cell level as well as logic gate level. The various combinational and sequential circuits like adder, comparator, multiplier, register and counter are designed and implemented on embryonic fabric using Verilog. The circuit performance is evaluated using simulation. The proposed PHsClone genetic algorithm (GA) design with parallel-pipeline approach is to achieve faster convergence. Four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator.

Keywords: Cartesian genetic programming, genetic algorithm, HsClone, embryonics, digital circuit

DOI: 10.3233/HIS-230012

Journal: International Journal of Hybrid Intelligent Systems, vol. 19, no. 3,4, pp. 183-200, 2023