Affiliations: [a] Instituto de Micro y Nanoelectrónica (IMNE), Universidad San Francisco de Quito (USFQ), Quito, Ecuador
Correspondence:
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Corresponding author: Ramiro Taco, Instituto de Micro y Nanoelectrónica (IMNE), Universidad San Francisco de Quito (USFQ), Quito 170901, Ecuador. Tel.: +593 994336194; E-mail: ramiro.taco@dimes.unical.it
Abstract: Spin-transfer torque magnetic random-access memory (STT-MRAM) has been demonstrated to be a leading candidate for on-chip memory technology. In this work, double-barrier magnetic tunnel junction (DMTJ) is exploited to define STT-MRAMs at the circuit-level (i.e. at the bitcell level). The DMTJ-based bitcells are built from tunnel-FET technology and benchmarked against a calibrated 10 nm-FinFET technology model. STT-MRAM bitcells operate in the ultra-low voltage domain, and are evaluated in terms of energy-efficiency and area. Simulation results points out that the tunnel-FET based solution is the most energy-efficient alternative, in terms of energy-delay-product (EDP), when evaluated at the 6𝜎 corner. Quantitatively, when compared against the FinFET-based design, the TFET-based bitcell exhibits 58% lower EDP, 40% better delay and 34% reduced writing energy. Finally, a leakage analysis was also carried out, showing that TFET-based STT-MRAM bitcells have lower leakage current as compared to the FinFET-based counterpart.
