Design of Reusable VHDL Component Using External Functions

Article type: Research Article

Authors: Štuikys, Vytautas

Affiliations: Kaunas University of Technology, Studentų 50, 3031 Kaunas, Lithuania. E-mail: vytas.stuikys@if.ktu.lt

Abstract: This paper describes a method how to represent and build a reusable VHDL component. By that component we can, for example, describe a family of the relative VHDL models. To represent the component, we use external functions as a mechanism to support a pre-processing and perform the instantiation of the component. A user interface, the constituent of the reusable component, serves for transferring parameters for the instantiation. We deliver a formal syntax of the functions and examples of their semantics. We describe the design of the reusable component as a procedure of transferring of: a) the intrinsic characteristics for a given family of domain objects and b) features from a given VHDL model(s). Those features require to be re-coded and extended with new ones by means of the external functions introduced. To test a reusable component, we use pre-processing and modelling.

Keywords: reusable component, template, VHDL model, pre-processing, external functions

DOI: 10.3233/INF-1998-9409

Journal: Informatica, vol. 9, no. 4, pp. 491-506, 1998