AN FPGA MOVE GENERATOR FOR THE GAME OF CHESS

Article type: Research Article

Authors: Boulé, Marc | Zilic, Zeljko^{; 1}

Affiliations: Montreal, Canada

Note: [1] McGill University, Department of Electrical Engineering, McConnell Engineering Building Room 633, 3480 University Street, Montreal, Quebec, Canada, H3A 2A7. Email: {mboul,zeljko}@macs.ece.mcgill.ca

Abstract: This article details the use of an FPGA (Field Programmable Gate Array) to increase the playing strength of the chess-playing program MBChess. The FPGA is a user-reconfigurable logic device well suited to the development of complex digital circuits. In this application, the FPGA is used to perform hardware move generation with implicit move ordering, a time-consuming operation when performed in software. A simpler inter-square connection protocol reduces the number of wires between chess squares, when compared to the Deep Blue design. The design also has the capability of generating checking moves separately, as well as indicating discovered checks: an important feature for good move ordering. Integration to the software’s transposition table and killer heuristic is demonstrated as well. The device is mounted on a card and inserted in the host computer where it is used as a coprocessor.

DOI: 10.3233/ICG-2002-25203

Journal: ICGA Journal, vol. 25, no. 2, pp. 85-94, 2002