Affiliations: School of Electrical, Computer and Energy Engineering, Arizona State University, USA | School of Informatics, University of Edinburgh, UK | School of Electrical, Computer and Energy Engineering, Arizona State University, USA | School of Computing, Informatics and Decision Systems Engineering, Arizona State University, USA | School of Electrical, Computer and Energy Engineering, Arizona State University, USA. Yu.Cao@asu.edu
Note: [] Address for correspondence: Computer and Energy Engineering, Arizona State University, USA
Abstract: Spiking neural P systems (in short, SN P systems) have been introduced as computing devices inspired by the structure and functioning of neural cells. The presence of unreliable components in SN P systems can be considered in many different aspects. In this paper we focus on two types of unreliability: the stochastic delays of the spiking rules and the stochastic loss of spikes. We propose the implementation of elementary SN P systems with DRAM-based CMOS circuits that are able to cope with these two forms of unreliability in an efficient way. The constructed bio-inspired circuits can be used to encode basic arithmetic modules.
