Abstract: Operations scheduling and Lookup Table (LUT) based technology mapping are fundamental problems of mapping designs onto an electronic device, such as a Field Programmable Gate Array. We present an approach to apply two optimizations consecutively. As first optimization, we apply several metaheuristic algorithms for multi-objective optimization at the High-Level Synthesis stage. As a second optimization, we realize reductions of LUTs at the Logic Synthesis stage. Several circuit designs are represented in a Data Flow Graph (DFG) and the experiments are carried out on the standard Mediabench benchmark. In the first optimization, we compared NSGA-II, FEMO, HypE, IBEA, SPEA2 and WSGA. Results have an average improvement 14.06% in occupied Area and 7.01% in Power consumption. Then, optimized DFG schedules are converted into Very High Description Language code using the Xilinx ISE Design Suite tool. Later, in the second optimization, The IMap algorithm is used to obtain combinational area reductions. Results show that 60% of the circuits are improved in comparison with the Xilinx ISE Design Suite.
