Abstract: In modern digital ICs, the increasing demand for performance and
throughput requires higher operating frequencies of hundreds of megahertz, and
in several cases exceeding the gigahertz range. Following the technology
scaling trends, this request will continue to rise, thus increasing the
electromagnetic interference (EMI) generated by electronic systems. The
enforcement of strict governmental regulations and international standards,
mainly (but not only) in the automotive domain, are driving new efforts towards
design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is
rapidly becoming a major concern for high-speed circuit and package designers.
The on-chip clock signals with fast rise/fall times are among the most
detrimental sources of electromagnetic (EM) noise, since not only they generate
radiated emissions, but they also have a large impact con the conducted
emissions, as the power rail noise localized in close proximity of the toggling
clock edges propagates to the board through the power and ground I/O pads. In
this work, we analyze the impact of different clock distribution solutions on
the spectral content of typical on-chip waveforms, in order to develop an
effective methodology for EMC-aware clock-tree synthesis, which globally
reduces the EM emissions. Our approach can be seamlessly integrated into a
typical design flow, and its effectiveness is demonstrated with experimental
results obtained from the clock distribution network of an industrial digital
design.